1. Field of the Invention
The present invention relates to a boosting circuit.
2. Description of the Related Art
In recent years, flash memories, which are non-volatile storage devices, are demanded to perform a data read operation and a data rewrite operation with a single power supply voltage or a low power supply voltage, and require a boosting circuit for supplying a positive boosting voltage or a negative boosting voltage on an ON chip when each operation is performed. Also in a CMOS process, a voltage generated by a boosting circuit is used as a power supply to improve a characteristic of an analog circuit.
FIG. 17 shows a configuration of a conventional boosting circuit (see U.S. Pat. No. 7,023,260). A boosting circuit 900 performs a boosting operation using two input clock signals CLK1 and CLK2 having phases different from each other. The boosting circuit 900 comprises boosting cells 141 and 161 that perform a boosting operation, charge transfer transistors 146 and 166 that transfer charges from input terminals INPUT 2A (or 2B) to output terminals OUTPUT 2A (or 2B), diode means 147 and 167 that are provided between the input terminal INPUT 2A (or 2B) and the output terminal OUTPUT 2A (or 2B), boosting capacitances 148 and 168 that are boosted, depending on the clock signals CLK1 and CLK2, inverters 150 and 170 that control the charge transfer transistor 146 (or 166) by switching the input terminal INPUT 2A (or 2B) of one boosting cell 141 (or 161) and the output terminal OUTPUT 2B (or 2A) of the other boosting cell 161 (or 141), depending on the potential of the output terminal OUTPUT 2A (or 2B), and outputs 152 and 172 of the inverters 150 and 170.
Next, an operation of the boosting circuit of FIG. 17 will be briefly described with reference to FIG. 18.
Initially, in a state at time T1, the clock signal CLK1 goes from “L” to “H”, so that the output terminal OUTPUT 2A of the boosting cell 141 is boosted. Since the output terminal OUTPUT 2A is boosted, the output 152 of the inverter 150 is switched from the voltage of the output terminal OUTPUT 2B of the boosting cell 161 to the voltage of the input terminal INPUT 2A of the boosting cell 141. Thereby, the gate voltage and the source voltage of the charge transfer transistor 146 have the same potential, so that the charge transfer transistor 146 is changed from the conductive state to the non-conductive state. Also, on the other hand, the clock signal CLK2 goes from “H” to “L”, so that the potential of the output terminal OUTPUT 2B of the boosting cell 161 is decreased. The decrease of the output terminal OUTPUT 2B causes the output 172 of the inverter 170 to switch from the voltage of the input terminal INPUT 2B of the boosting cell 161 to the voltage of the output terminal OUTPUT 2A of the boosting cell 141. Thereby, the gate voltage of the charge transfer transistor 166 becomes higher than the source voltage thereof, so that the charge transfer transistor 166 is changed from the non-conductive state to the conductive state, and therefore, charges are transferred from the input terminal INPUT 2B to the output terminal OUTPUT 2B.
Next, at time T2, an operation reverse to that of the boosting cells 141 and 161 using the clock signals CLK1 and CLK2 at time T1 is performed, so that charges are transferred from the input terminal INPUT 2A to the output terminal OUTPUT 2A in the boosting cell 141, and the output terminal OUTPUT 2B is boosted in the boosting cell 161.
Thereafter, the operations described above are repeatedly performed, thereby performing a boosting operation.